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General-purpose timer (TIMx)
RM0008
14.4.16
TIMx capture/compare register 4 (TIMx_CCR4)
Address offset: 0x40
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
CCR4[15:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:0 CCR4[15:0] : Capture/Compare value
1/ if CC4 channel is configured as output (CC4S bits):
CCR4 is the value to be loaded in the actual capture/compare 4 register (preload value).
It is loaded permanently if the preload feature is not selected in the TIMx_CCMR4 register (bit
OC4PE). Else the preload value is copied in the active capture/compare 4 register when an
update event occurs.
The active capture/compare register contains the value to be compared to the counter
TIMx_CNT and signalled on OC4 output.
2/ if CC4 channel is configured as input (CC4S bits in TIMx_CCMR4 register):
CCR4 is the counter value transferred by the last input capture 4 event (IC4).
14.4.17
TIMx DMA control register (TIMx_DCR)
Address offset: 0x48
Reset value: 0x0000
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Reserved
DBL[4:0]
Reserved
DBA[4:0]
rw
rw
rw
rw
rw
rw
rw
rw
rw
rw
Bits 15:13 Reserved, always read as 0
Bits 12:8 DBL[4:0] : DMA burst length
This 5-bits vector defines the length of DMA transfers (the timer recognizes a burst transfer
when a read or a write access is done to the TIMx_DMAR address), i.e. the number of bytes to
be transferred.
00000: 1 byte,
00001: 2 bytes,
00010: 3 bytes,
...
10001: 18 bytes.
Bits 7:5 Reserved, always read as 0
Bits 4:0 DBA[4:0] : DMA base address
This 5-bit vector defines the base-address for DMA transfers (when read/write access are
done through the TIMx_DMAR address). DBA is defined as an offset starting from the
address of the TIMx_CR1 register.
Example:
00000: TIMx_CR1,
00001: TIMx_CR2,
00010: TIMx_SMCR,
...
372/995
Doc ID 13902 Rev 9
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